NXP Semiconductors /MIMXRT1052 /SEMC /MCR

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Interpret as MCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SWRST)SWRST 0 (MDIS_0)MDIS 0 (DQSMD_0)DQSMD 0 (WPOL0_0)WPOL0 0 (WPOL1_0)WPOL1 0CTO0 (BTO_0)BTO

WPOL0=WPOL0_0, BTO=BTO_0, DQSMD=DQSMD_0, MDIS=MDIS_0, WPOL1=WPOL1_0

Description

Module Control Register

Fields

SWRST

Software Reset

MDIS

Module Disable

0 (MDIS_0): Module enabled

1 (MDIS_1): Module disabled.

DQSMD

DQS (read strobe) mode

0 (DQSMD_0): Dummy read strobe loopbacked internally

1 (DQSMD_1): Dummy read strobe loopbacked from DQS pad

WPOL0

WAIT/RDY# polarity for NOR/PSRAM

0 (WPOL0_0): Low active

1 (WPOL0_1): High active

WPOL1

WAIT/RDY# polarity for NAND

0 (WPOL1_0): Low active

1 (WPOL1_1): High active

CTO

Command Execution timeout cycles

BTO

Bus timeout cycles

0 (BTO_0): 255*1

1 (BTO_1): 2552 - 2552^30

2 (BTO_2): 2552 - 2552^30

3 (BTO_3): 2552 - 2552^30

4 (BTO_4): 2552 - 2552^30

5 (BTO_5): 2552 - 2552^30

6 (BTO_6): 2552 - 2552^30

7 (BTO_7): 2552 - 2552^30

8 (BTO_8): 2552 - 2552^30

9 (BTO_9): 2552 - 2552^30

31 (BTO_31): 255*2^31

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